1. Field of the Invention
The present invention relates to an analog capacitor, and a method of fabricating the same, and more particularly, to an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same.
2. Description of the Related Art
An analog capacitor is one element of a device typically used in an analog-to-digital converter (ADC), a RF device, a switching capacitor filter, a CMOS image sensor (CIS), and the like. The analog capacitor is a capacitor which obtains bits and operates based on the fact that the quantity of charge stored in the electrodes on both ends of a dielectric layer varies corresponding to the change of an applied voltage.
When a voltage (V) is applied on a capacitor, the quantity of charge (Q) stored in the electrodes of both ends of a dielectric layer can be given by Equation 1.Q=C×V,  [Equation 1]
where C is a capacitance of the capacitor.
In the case in which the capacitance (C) has a constant value, the quantity of charge (Q) is linearly increased in proportion to the voltage (V). The quantity of charge (Q) stored in the capacitor is constant, when the voltage (V) is fixed. Therefore, the voltage can be divided within the range of an operating voltage of a capacitor, and the quantity of charge corresponding to each divided voltage can be used as one bit.
In order to obtain high bits in an analog capacitor, the difference of the quantities of charge corresponding to each divided voltage should be large and constant. For this purpose, the dielectric layer used in an analog capacitor requires that its voltage coefficient of capacitance (VCC), i.e., the change of the capacitance in variance with voltage, be low, its capacitance be large, and its leakage current be low.
With the increased integration in semiconductor devices , the capacitor size is increasingly scaled down. Therefore, in order to prevent the reduction of the capacitance corresponding to the size decrease of the capacitor, a high-k dielectric layer is used. A dielectric layer having a dielectric constant higher than or equal to 8 is defined as a high-k dielectric layer.
The capacitance of a dielectric layer typically depends on a voltage. That is, capacitance ((C(V)) can be indicated by a function of applied voltage (V), and can be fitted as a quadratic function, which is given by Equation 2.C(V)=C(0)×(a×V2+b×V+1)  [Equation 2]
where C(0) is a capacitance of a capacitor with applied voltage 0V, a is a quadratic coefficient of VCC, and b is a linear coefficient of VCC. Thus, in order to have a low value of VCC, a and b should be close to zero.
The quadratic coefficient a is known to be related to the interfacial characteristics of the electrodes and the dielectric layer of the capacitor. That is, if a depletion occurs in the electrodes when a voltage is applied, the quadratic coefficient has a negative value. In contrast, if electrons penetrate into the dielectric layer thereby to reduce the effective thickness of the dielectric layer, the quadratic coefficient has a positive value.
Therefore, the dielectric layer used in the analog capacitor as a high-k dielectric layer requires that its leakage current be low and that the absolute value of the quadratic coefficient of VCC be low. However, it is difficult to satisfy the leakage current characteristics and the VCC characteristics simultaneously using a single dielectric layer.